A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


SEU Hardening of Field Programmable Gate Arrays (FPGAs) For Space Applications and Device Characterization

R. Katz
NASA/Goddard Space Flight Center, Greenbelt, MD 20771

R. Barto
INTELSAT, Palo Alto, CA 94303

P. McKerracher
Johns Hopkins University/Applied Physics Laboratory, Laurel, MD 20723

R. Koga
The Aerospace Corporation, El Segundo, CA 90245


Field Programmable Date Arrays (FPGAs) are being used in space applications because of attractive attributes: good density, moderate speed, low cost, and quick turn-around time. However, these devices are susceptible to Single Event Upsets (SEUs). An approach using triple modular redundancy (TMR) and feedback was developed for flip-flop hardening in these devices. Test data showed excellent results for this circuit topology. Total dose and Single Event Effect (SEE) testing have been performed on recently released technologies. Failures are analyzed and test methodology is discussed.

Table of Contents

I. Introduction
II. Objectives
III. Proposed SEU Hardening Techniques

    A. Basic Method and D Flip-Flop
    B. Register Element and J-K
    C. Asynchronous Logic
    D. Effective Hardening of the Clock Tree

IV. SEU Rejection Analysis

    A. Analysis of Error Correcting Capability (Idealized)
    B. Technology Dependent Parameters Effecting SEU Rejection

V. Design Issues

    A. Clock Skew
    B. External Interfacing

VI. Test Devices and Techniques

    A. Devices
    B. Test Techniques

VII. Test Results and Device Analysis

    A. TMR Evaluation
    B. Device SEE Characteristics and Analysis
    C. Device Total Ionizing Dose Characterization

VIII. Analysis and Application Information

    A. A1020B
    B. A1280A

    1. I/O Latches
    2. Internal Modules
    3. Latchup and Part Damage

    C. SEE Comparison Between Actel Technologies
    D. Evaluation of TMR Structures
    E. Total Dose Performance

IX. Conclusion

List of Figures

Figure 1. Compact TMR with Hardened Clock Tree and Voter

Figure 2. TMRA2.C S/N 4 IDDQ Data

Figure 3. TD1280 ICC Response

Figure 4. TD1280 ICC Response


Design techniques to reduce SEU sensitivity have been presented and where possible analyzed. Test results have shown that these techniques result in a substantial improvement in the SEU rate.

The latest generation of Actel A1020B and A1280A FPGAs using 1.0 Ám technology were tested for SEE and total dose. While previous SEE testing have shown the Actel parts to be immune from destructive effects, latchup was observed in the A1020B and damage was detected in one lot of A1280A parts. TID testing results were mixed: the A1020B performed well while the A1280A had large currents at the 10 kRad(Si) step. Additionally, transient current spikes were observed both during radiation exposure and monitoring. While the effects of these transients has not been determined, 900 mA spikes are in general not good for either the device or the power system. Continuous current monitoring of the devices for TIB testing and annealing should be performed.

Additional testing and analysis is needed to further characterize new technology parts. The advantages of the FPGA to spacecraft electronic designs warrants additional investigation with the goal being recommendations to the manufacturer or the development of adequate lot screening procedures.

Last Revised February 03, 2010
Digital Engineering Institute
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