NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Briefing: RT54SX-S, RTSX-SU, RTAX-S, and Eclipse FPGAs for Spaceborne Application

On Wednesday May 10, 2006, a briefing was held on the Actel RT54SX-S, RTSX-SU, RTAX-S, and Eclipse FPGAs for spaceborne application at the NASA Goddard Space Flight Center in Greenbelt, MD.  The briefing started at 9:30 am in the Building 8 auditorium.

This briefing continued the on-going discussions, held quarterly, and cover the latest in test results, analyses, and design information.

Two companion meetings were held.  There was the "RTAX-S Boot Camp" on Tuesday, May 9 and the "Eclipse Boot Camp" on Thursday, May 11.  Both boot camps were held on-site at the NASA Goddard Space Flight Center.

Please use the registration form below to register for all events.

Regards,

-- rk

Register for seminar notification e-mail list.

Schedule

•  9:30 am  Meeting starts

• 12:30 pm  Lunch.  Buildings 1 and 21 have cafeterias

•  1:45 pm  Meeting resumes

• Work until we're done (it will be late, based on our previous briefings).

Snacks for breaks will be provided, courtesy of the NASA Office of Logic Design.  Each participant is responsible for their own lunch and dinner (federal rules).  Coffee and tea will be provided.

Agenda:

10: "Introduction," Rich Katz, NASA Office of Logic Design
11: "RTAX-S Notes," Rich Katz, NASA Office of Logic Design
12: "DPA: Aeroflex Eclipse," Rich Katz, NASA Office of Logic Design

20: "LOLA 1553 Chip Overview," Rod Barto, NASA Office of Logic Design

Reliability Testing and Data

• 31: "NASA RTSX-SU Test Update," Presented by Daniel Elftmann, Actel

• 32: "Actel RTSX-SU FPGA Reliability Summary," Daniel Elftmann, Actel

• 33: "Aeroflex RadHard FPGA Reliability Update," Gerald Matia, Aeroflex

• 34: "Aerospace Space Qualification Testing: Status of Actel RTSX-SU Field Programmable Gate Arrays," Larry Harzstark, The Aerospace Corporation

• 35: "Actel RTAX-S FPGA Reliability Summary," Daniel Elftmann, Actel 

Radiation Testing 

• 41: "Radiation Characterization of a Hardened 0.22 μm Anti-Fuse Field Programmable Gate Array," Presented by Ken LaBel, NASA Goddard Space Flight Center

• 42: "High Speed Testing of the Aeroflex RadHard Eclipse FPGA," Presented by Ken LaBel, NASA Goddard Space Flight Center

• 43: "RTAX-S Single Event Effects (SEE) High-Speed Test Results – Update," Ken LaBel, NASA Goddard Space Flight Center

---

Previous Briefings and References

• January 11, 2006

• AX and RTAX-S FPGA Bond Wires

• 2005 MAPLD International Conference, See Proceedings

• May 11, 2005

• February 16, 2005

• September 22, 2004

• July 13, 2004

• April 13, 2004

Independent NASA Test of Actel SX-A, SX-S, and SX-SU Field Programmable Gate Arrays (FPGAs)

Related Meetings
RTAX-S Boot Camp ... (Charts)	Eclipse Boot Camp     (Charts)
Abstract The Actel RTAX-S FPGA provides designers several features such as increased gate densities, embedded RAM blocks, an I/O structure that supports multiple I/O standards with high user I/O count, SET-hardened clocks, and SEU protected flip-flops. Additionally Actel provides a set of design tools to optimize designs for specific application needs. This session will introduce users to RTAX-S FPGA technology and the design techniques for space flight applications.	Abstract The Aeroflex RadHard Eclipse Bootcamp will offer users an introduction to the Aeroflex RadHard FPGA and the Quickworks FPGA development toolset.  The UT6325 FPGA provides robust clocking networks, fully configurable radiation hardened memory, support for multiple I/O standards and RadHard registers in the FPGA fabric and I/O cells.  Rapid prototyping is supported through a range of die/package options from plastic to fully space flight qualified.
Agenda RTAX-S family overview RTAX-S Architecture SuperCluster R-cell with TMR C-cell and Carry Logic Clock Networks RAM / FIFO I/Os JTAG SmartGen Macro Builder Synthesis Constraints and Attributes Entering Timing Constraints in Designer Floorplanning with ChipPlanner Designer Layout Options Tips & Techniques for Timing Closure	Agenda RadHard Eclipse Overview Logic Cell, RAM, I/O Cells Routing Resource ViaLinkTM Process Clocks, Set, Clear Packaging/Rapid Prototyping Design Considerations: How to best use the Aeroflex RadHard Eclipse FPGA Do’s and Don’t’s TMR Design SSO and Power on Reset, ESD Design System Introduction/Pre-Lab: QuickWorksTM Design Entry Synthesis Simulation Place and Route Static Timing Analysis Programming Hands on Laboratory – Implementation of a Simple Design

Logistics

• Maps and Driving Directions

• Lodging

All attendees should complete the registration form below and observe the following dates.  On-site NASA personnel should also register to aid in event planning and notification of any logistical changes.

• Non-US citizens: April 12, 2006

• US citizens:     May    3, 2006

• Webex access:    May    5, 2006

Recording of this meeting will not be permitted.  Meeting notes will be distributed via http://klabs.org.

Registration  Form for May, 2006, FPGA Briefing

1. Registration Type	On-site, I have NASA access Need access to NASA GSFC Webex connection needed Webex, colleague has requested connection
2. First Name
3. Last Name
4. Your E-mail
5. Telephone Number
6. Company Name
7. Citizenship	Citizenship Status I am a US citizen I am not a US citizen REMEMBER TO FILL THIS FIELD OUT
8. RTAX-S Boot Camp (May 9)	select Attending RTAX-S Boot Camp Not Attending RTAX-S Boot Camp
9. FPGA Briefing (May 10)	select Attending FPGA Briefing Not Attending FPGA Briefing
10. Eclipse Boot Camp (May 11)	select Attending Eclipse Boot Camp Not Attending Eclipse Boot Camp
11. NASA GSFC tour (if available)	select Attending GSFC Tour Not Attending GSFC Tour

Comments, notes, and additional information.

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Last Revised: February 03, 2010
Web Grunt: Richard Katz