PROGRAMMABLE TECHNOLOGIES WEB SITE

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


MAPLD 99 Conference Schedule

 

  Monday - 27th Tuesday - 28th Wednesday -29th Thursday - 30th
7:30 AM     Check-In and Continental Breakfast Continental Breakfast Parallel Session Continental Breakfast
7:35 AM    
7:40 AM    
7:45 AM    
7:50 AM    
7:55 AM    
8:00 AM    
8:05 AM    
8:10 AM    
8:15 AM    
8:20 AM    
8:25 AM    
8:30 AM     C0: Katz - FPGAs in Space Environment and Design Techniques F0:Dunham - "Gigasample Image and Signal Processing via Reconfigurable Computing" D0: Sandi Habinc - "Designing Space Applications Using Synthesizable Cores"
8:35 AM    
8:40 AM    
8:45 AM     Welcome - Dr. Krimigis
8:50 AM    
8:55 AM     Conference Opening Remarks
9:00 AM    
9:05 AM     A0: Dr. Ralph McNutt - JHU/APL Space Exploration Beyond 2020
9:10 AM    
9:15 AM     C1: Wang - "Total dose and SEE of Metal-to-Metal Antifuse FPGA" F4:Hunsberger - "Secure Reconfiguration of Context Switching FPGAs" D1: Conde - "Adaptive Instrument Module through Programmable Logic"
9:20 AM    
9:25 AM    
9:30 AM    
9:35 AM    
9:40 AM     Poster and Exhibits Pause D2:Kleyner "Reconfigurable, SoC, High-Speed Data Processing and Handling Electronics"
9:45 AM    
9:50 AM     A1: Wagner - "One Gigasample Per Second Data Acquisition Using Available Gate Array Technology"
9:55 AM    
10:00 AM    
10:05 AM     Poster and Exhibits
10:10 AM     F3: Jensen - "Secure Reconfigurable Computing"
10:15 AM     Poster and Exhibits
10:20 AM    
10:25 AM     C2: Caffrey - "Radiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing"
10:30 AM     D3: Lach - "Runtime Logic and Interconnect Fault Recovery on Diverse FPGA Architectures"
10:35 AM     Pause
10:40 AM    
10:45 AM    
10:50 AM     C3: Swift - "Results from Recent Radiation Testing of the Samsung 128Mb Flash Memory" F1: Zaino - "An FPGA Based Adaptive Computing Implementation of Chirp Signal Detection"
10:55 AM     D4: Doumar - "Fault Tolerant FPGAs by Shifting the Configuration Data"
11:00 AM     A2: Vladimirova - "FPGA Implementation of Sine and Cosine Generators Using the CORDIC Algorithm"
11:05 AM    
11:10 AM    
11:15 AM     C4: Barto - "SEU Induced Anomalous Operation of Voted Ripple Clocks"  
11:20 AM       D5A: Kim - "Factoring Large Numbers with a Prog. Hardware Implementation of Sieving"
11:25 AM     A3: Bezerra - "A VHDL implementation of an On-board ACF Application Targeting FPGAs"  
11:30 AM      
11:35 AM      
11:40 AM     Pause  
11:45 AM     E7: Chang - "Adaptive Computing in NASA Multi-Spectral Image Processing"   Conference Ends
11:50 AM     A4: Katz - "Logic Design Pathology and Space Flight Electronics"  
11:55 AM      
12:00 PM Industrial Exhibit and Poster Setup    
12:05 PM    
12:10 PM   Lunch, Posters, and Industrial Exhibits.    
12:15 PM   Lunch, Posters, and Industrial Exhibits.    
12:20 PM      
12:25 PM      
12:30 PM      
12:35 PM      
12:40 PM      
12:45 PM      
12:50 PM      
12:55 PM      
1:00 PM      
1:05 PM      
1:10 PM      
1:15 PM      
1:20 PM      
1:25 PM      
1:30 PM   B0: McCollum Programmable Elements and Their Impact on FPGA Architecture, Performance, and Radiation Hardness E0: Hutchings - Configurable Computing: Past, Present and Future    
1:35 PM      
1:40 PM      
1:45 PM      
1:50 PM      
1:55 PM      
2:00 PM      
2:05 PM      
2:10 PM      
2:15 PM   B1: Gibbons - "Use of FPGA's in critical space flight applications-A Hard Lesson" E1: Gloster - "Evaluating Placement Algorithms for Run-Time Reconfigurable Systems"    
2:20 PM      
2:25 PM      
2:30 PM      
2:35 PM      
2:40 PM   B2A   - Carmichael - "SEU Mitigation Techniques for Virtex FPGAs in Space Applications" E2: Natarajan - "Automatic Mapping of Khoros-based Applications to Adaptive Computing Systems"    
2:45 PM      
2:50 PM      
2:55 PM      
3:00 PM      
3:05 PM   Poster and Exhibits Poster and Exhibits    
3:10 PM      
3:15 PM      
3:20 PM      
3:25 PM      
3:30 PM      
3:35 PM      
3:40 PM      
3:45 PM      
3:50 PM   B3: Edwards - "Analog Module Architecture for Space Qualified Field Programmable Mixed Signal Arrays" E3: Kumar - "Adapters"    
3:55 PM      
4:00 PM Check-In, Reception, and AIAA Chapter Meeting    
4:05 PM    
4:10 PM    
4:15 PM B4: Cantle - B4: "A Foundation Architecture for Elevating DSP in FPGAs" E4: Bondalapati "Mapping Applications onto Reconfigurable Architectures using Dynamic Programming"    
4:20 PM    
4:25 PM    
4:30 PM    
4:35 PM    
4:40 PM B5: Zhang - "Laser-formed Vertical Metallic Link and Potential Implementation in Digital Logic Integration" E5: Dandalis - "Run-time Mapping of Graph-Problem Instances onto Reconfigurable Hardware"    
4:45 PM    
4:50 PM    
4:55 PM    
5:00 PM    
5:05 PM B6: Speers - "0.25 UM Flash Memory Based FPGA for Space Applications" E6: Neema - "Adaptive Computing and Run-time Reconfiguration"    
5:10 PM    
5:15 PM    
5:20 PM    
5:25 PM    
5:30 PM Dinner, Posters, Industrial Exhibits. Dinner, Posters, Industrial Exhibits.    
5:35 PM    
5:40 PM    
5:45 PM    
5:50 PM    
5:55 PM    
6:00 PM    
6:05 PM      
6:10 PM      
6:15 PM      
6:20 PM      
6:25 PM      
6:30 PM      
6:35 PM      
6:40 PM      
6:45 PM   Dr. Don DeVoe, University of Maryland at College Park "Micro Electro Mechanical Systems (MEMS)" Panel Session - "Architecture, Technologies and Design Methodologies for 2005 and Beyond"    
6:50 PM      
6:55 PM      
7:00 PM      
7:05 PM      
7:10 PM      
7:15 PM      
7:20 PM      
7:25 PM      

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Last Revised: January 09, 2002
Digital Engineering Institute
Web Grunt: Richard Katz