Dino Caporossi
Hier Design, Inc.Abstract
High-end FPGA designers are now facing the same types of problems that have plagued ASIC designers of the past including lengthy, repeated place and route runs, unpredictable route times, and difficulty maintaining performance during frequent design iterations. These problems can delay or even obstruct design completion, resulting in increased engineering costs and time-to-market. This paper will describe an ASIC-style methodology for FPGAs that gives the designer the capability to design hierarchically, or using a block-based approach. It also enables them to analyze, detect and correct potential implementation problems earlier in the design cycle.
When designers using a flat methodology make changes to a given logic block, they must redo place and route for the entire design. With an ASIC-style design methodology, designers use hierarchy to reduce place and route time. By breaking their designs into smaller pieces, or blocks, they can just run place and route on the block or blocks that have changed, leaving the rest intact. Place and route algorithms also are more efficient and faster when operating on smaller blocks, rather than large flattened netlists.
When designing using a flat methodology, a designer often tries to reach timing goals by trying multiple routing runs, each with different random seed values, hoping that one of them will produce a design with adequate performance. A hierarchical methodology provides a more deterministic process by enabling designers to define area groups to steer place and route toward acceptable timing.
Designers can also lock placement results for individual blocks that already meet timing, so that subsequent place and route iterations do not change their performance.
Designers of large FPGAs usually iterate the physical implementation many times. One reason for this is that they are trying to cope with too many simultaneous requirements. Such requirements include minimizing routing congestion, maximizing utilization, optimizing I/O placement, reducing power and reaching timing goals. Worse, many of the requirements are interrelated, so making design changes to achieve one requirement often causes problems in achieving several others.
ASIC-style methodologies help designers reach their requirements more easily, prior to place and route, through early design analysis coupled with floorplanning. By doing analysis early in the design cycle, such as connectivity and timing, designers can detect problems that could prevent them from meeting design requirements.
Floorplanning then enables them to make up-front adjustments to the design to alleviate these problems so that, after place and route, requirements are more likely to be met, thereby reducing the number and length of place and route iterations.
Designers of complex FPGAs can also have difficulty meeting timing requirements due to such problems as long critical paths spanning hierarchy, complex clocking and high fan-out. ASIC designers have been successfully overcoming these kinds of problems for many years using static timing analysis and floorplanning. Static timing analysis shows critical paths so that designers can fix them using floorplanning by specifying constraints or rearranging the path instances.
FPGA designers can also have trouble meeting utilization goals. In some cases, it is desirable to crowd as much logic into a given device as possible to meet production volume requirements, and in others it is desirable to leave some amount of spare space in the device to accommodate bug fixes, naturally-occurring design changes, engineering change orders (ECOs), or even future planned field upgrades. Block-based, hierarchical design techniques make it easier to control utilization. Designers can continually set block-level utilization controls higher and higher until place and route fails, which means maximum utilization has been achieved. Designers who need to leave some amount of spare space in their designs can use a lower utilization setting in blocks where the extra space is desired.
Like ASIC designers, FPGA designers can shorten design time by working as a team and reusing intellectual property (IP) from previous designs. An ASIC-style hierarchical methodology enables this kind of teamwork. Designers can use a block-based approach to divide their work into more manageable pieces and assign responsibilities of designing them to individual team members.
Designers can reuse blocks from previous designs, or even purchase them from a third party to save design and verification time.
Further, designers can begin the physical implementation process with blocks as they are designed, rather than waiting for the whole design to be completed first.
By employing ASIC-style methodologies, designers can fully characterize their design blocks by freezing the placement within them such that power, timing and other characteristics remain constant so that they can be reused with consistent results in similar FPGA devices. ASIC designers refer to this type of design as a system-on-a-chip (SOC) methodology, and it offers the same great benefits to designers of complex FPGAs.
This methodology is particularly valuable for ASIC designers using FPGAs for prototyping who want to reduce their overall verification time. Designers can connect IP blocks together whose timing has already been pre-characterized using analysis and floorplanning.
This enables designers to more quickly assemble ASIC prototypes that meet timing requirements.
Summary
FPGAs have become so complex that designers are now encountering ASIC-size design problems such as long place and route time, too many design iterations, and difficulty reaching and maintaining physical design requirements such as timing. In short, designing in flattened mode has become a major bottleneck.
FPGA designers can overcome these problems by adopting proven ASIC-style design methodologies including hierarchical design, which enables designers to make fast incremental changes, and early analysis, which enables designers to fix problems prior to place and route. They can closely control utilization, packing designs ever tighter, or leaving extra room for bug fixes, ECOs, or planned upgrades for products that have a long field or shelf life. Finally, designers can work as a team and shorten design and verification time by reusing blocks of pre-characterized IP.