Mitigation of Single Event Upset (SEU) by Virtual Redundancy
in Design

by Kaijie Wu*, Polytechnic University, Brooklyn and Jake
Karrfalt, Alternative System Concepts, Inc.

* presenter

Radiation induced Single Event Upsets (SEU) in electronic
devices and components, such as encountered in space
environments, have traditionally been costly to overcome.
One current approach uses triple modular redundancy (TMR),
where each processing and control circuit path is tripled
and voted, such that when the outputs of the three circuit
paths are not the same, assuming single failure, the odd
circuit is disregarded.

As an SBIR project a low-cost automatic design methodology
for achieving radiation hardness was proposed. Through this
new algorithmic approach we obtained results similar to TMR.
We proved that the algorithmic approach to design can
improve radiation tolerance. We developed and tested models
of some actual components employing the application of
virtual redundancy to error detection, error correction,
error diagnosis, and circuit reconfiguration as a means of
concurrent error recovery.  In Virtual Redundancy the same
element is used during idle cycles to re-compute processing
functions for concurrent error detection (CED).  If the two
results do not agree, the computation returns to a
checkpoint, and is recalculated and verified.  It is thus
possible to identify the faulty functional unit.  Idle
cycles in the design are used for this purpose.  Two
traditional circuits were selected for analysis and
simulation of the results of adding virtual redundancy to
the design.  The RC6 encryption algorithm was the first
example used to validate through simulation the Virtual
Redundancy concept.  Simulation results, which include
injected errors, were effective in proving the concept, yet
simple enough to be suitable for detailed analysis. The
second example used was to validate the virtual redundancy
concept, including response to injected errors, was the FIR
filter, another useful design with greater complexity than
the RC6 encryption algorithm, providing a more stringent
test of idle cycle based CED.  The feasibility of developing
a tool to create Virtual Redundancy in circuits was proven
through simulation during this Phase I program, with a
demonstration at SMDC in Huntsville, Alabama on September
12, 2000.

The Virtual Redundancy approach is more economical, requires
less power, and is more reliable, when compared with
traditional TMR, because there is no need to triple the
circuit. If a pattern of faults is detected, this circuit
can conceivably be used to repair itself.  Except for a
minor increase in area and power, a radiation hardened
circuit can be produced for the same cost, area and power as
a non rad-hard commercial component.  This has huge payoff
in secondary weight effects for power supplies in space
applications, but can be used to improve reliability at
minimal cost in virtually any application.