Cost & Performance Measures for Optimizing Configurable Computer Architectures

Chandru Mirchandani
Lockheed Martin Space Operations
NASA/Goddard Space Flight Center
E-mail: chandru@kong.gsfc.nasa.gov
Tel: (301) 286-7967


Abstract

The advent of very-high speed re-configurable elements has opened a plethora
of applications both in private industry and the public sector.  The fact 
that configurable architectures can be designed to be very quickly adaptable
to changing requirements reduces design and development costs for new systems.
However, the need for fast turn-around of systems could lead to lowering 
performance and reliability goals for the new system to meet these schedules.
The process, by which the different tasks are allocated within the 
configurable elements, or between the configurable elements and the
traditional CPU, is not as straightforward as one would assume.  In
fact, Kimura in his paper, "Parallel Viterbi Decoding Implementation
By Multi-Microprocessors" - IEICE Transactions On Communications, stated it
very succinctly when he picked on the Viterbi algorithm, "The Viterbi 
algorithm is a well-established technique for channel and source decoding
in high performance digital communication systems. However, excessive time
consumption makes it difficult to design an efficient high-speed decoder for
practical application".  He went on to describe the implementation of Parallel
Viterbi algorithm by multi-microprocessors, implemented using a combination of
tables and calculations.  In addition to task and architecture selection, the
designers have to select the measures to evaluate these choices and the
criteria for qualifying the same.


Introduction

Performance and cost are underlying drivers in the NASA R&D environment,
consequently NASA has been actively investigating the option to develop newer
processes and methods using new emerging technology to operate effectively at
very high data rates.  Traditionally, these data rates required high cost,
customized hardware and software.  In producing all-digital systems operating
at data rates of 150 Megabits per second and higher, developers have to make
a trade-off between size versus power, schedule versus performance and custom
versus standard design options.  Through advancements in digital processing
algorithms and hardware it is now possible to develop hybrid systems that use
the speed and flexibility of FPGA elements and the compute power of the 
traditional workstation.  The reliability of a system increases with the
number of distinct physical components and the traditional approach of a
system designed within its own enclosure is composed of functional modules
that exist as different pieces within the system.  These may be off-the-shelf
components with their own high-reliability and performance numbers, but taken
as a whole with the other components within a module degrades the overall
system reliability.  The compression of the system on to a single board
solution or conceivably a single-chip solution will increase the reliability
of the system.  Albeit the complexity of the system has increased, but with
low-replication cost, larger samples can be used in the design of experiments
to obtain true reliability numbers, which would help to easily assess the
causes and correct for them.  For example, digitally re-programmable devices
afford the luxury of fast turn-around that custom pieces of equipment do not
have.  The all-digital receiver, currently being developed at NASA, offers
five distinct advantages over the traditional analog counterpart. They are
far less expensive to reproduce (typically at least an order of magnitude);
are much smaller in size and weight, consume far less power, have increased
flexibility, and have increased reliability.  

This paper will describe one model for optimizing the performance and
reliability of a new system.  The model defines cost-performance and 
cost-reliability measures.  The paper provides an overview of how a design
process using re-configurable elements is accomplished.  The process
highlights the cost, performance benefits of a design currently being
developed against currently available alternatives.  The criteria for
selecting performance and reliability metrics are cost optimization.  This
paper will demonstrate the improvement in reliability and performance as
applied to an image processing application used in the space industry, when
this optimization process is used.

Background

The task at hand is to first define the basic architectural differences
between the traditional computing task model and the re-configurable
computing paradigm.  The next step in the process is to describe how best
one can make use of this emerging technology to optimize the implementation
of the task model.  To understand the implementation approach, the paper
exemplifies a hypothetical system in which source data is extracted from
standardized packets and processed through some level 1 processing algorithm
for information extraction, which in this case is an image.    The system 
may be implemented in one of three ways, namely: 

(1) Complete software solution, whereby the software system resides on a
workstation with adequate compute power to ingest, process, distribute and
monitor the process.

(2) Complete hardware solution for the ingest, process and distribution
functions in custom hardware, with adequate control and monitor functionality

(3) Hybrid solution of custom hardware and traditional software

(4) Hybrid solution of software and Re-configurable computing elements

The system that is described in the paper uses the fourth option to realize
the system, and hence it is an allocation of the tasks within the system that
have to be optimized.

The traditional software model for a system has been discussed in length by
Littlewood & Myers [10].  The approach used here will develop a performance
model and a reliability dependence model for the system.  Subsequently, 
metrics will be developed to describe how sub-processes should be allocated
between the re-configurable elements and traditional software.