A MIXED-SIGNAL PROGRAMMABLE ARRAY USING ANTIFUSE INTERCONNECT

     R. Timothy Edwards, Kim Strohbehn, and Stephen E. Jaskulek
     Johns Hopkins University Applied Physics Laboratory
     Laurel, Maryland


   The ability to use radiation-tolerant programmable digital logic parts in
   hardware intended for use in space missions provides significant cost
   savings.  The savings result partly from shorter design cycles and lower
   risk, but mostly from reduced parts acquisition and flight qualification
   costs.  Without these parts, many projects would be unable to afford
   custom gate array implementations, and would be forced to resort to
   discrete component designs with the accompanying increase of system size,
   mass, and power consumption.

   A similar situation exists in the mixed-signal field today.  Almost all
   spacecraft contain numerous moderate-performance analog and digital
   processing and I/O circuits.  These circuits, used for applications such
   as status monitoring, motor and temperature control, and signal conditioning
   and processing, are widely distributed throughout the spacecraft.
   Traditionally, these mixed-signal circuits have been implemented almost
   exclusively using discrete components, because the cost savings are not
   significant enough to justify a custom ASIC design.  However, the resources
   used by such circuits, including mass, power, and volume, add up very
   quickly.  The ability to implement such designs using general-purpose,
   programmable analog or mixed-signal arrays would be advantageous in all
   respects, analogous to the advantages gained using a Field-Programmable
   Gate Array (FPGA) for digital circuits:  lower parts acquisition and
   qualification costs, higher levels of integration, lower power consumption,
   fast turn-around time for design cycles, and improved reliability.

   Field-Programmable Analog and Mixed-Signal Arrays (FPAAs and FPMAs) address 
   this need for quick turnaround time in analog flight hardware development.
   Whereas FPGA architectures typically consist of essential basic
   combinatorial and sequential logic blocks (flip-flops and mux-based logic,
   for example), FPAAs vary widely in the choice of the core programmable
   analog module.  The granularity of the module tends to be a function of the
   performance of the interconnect:  Slower (high-resistance, on the order of
   1 kOhm) interconnect types (such as SRAM- or EPROM-based) can seriously
   degrade analog perforamance if inserted at arbitrary points in an analog
   design.  Thus, modules for RAM-based analog arrays tend to have a large
   granularity such as an entire filter section and allow interconnect
   programmability only at certain critical points, such as between filter
   sections or in series with the resistor in the amplifier's feedback loop.
   Faster (lower-resistance) interconnect types allow a finer module
   granularity, to the limit of gate array architectures, which allow
   programmability at the level of individual transistors, but does not solve   
   the stated problem of quick turnaround time and flight qualification.  In
   between, antifuse interconnect (with resistance as low as 15 to 20 Ohms)
   offers a good tradeoff between functionality and performance on one hand
   and quick development time and pre-flight qualification on the other.

   In the past year, we have entered into a cooperative agreement with
   Actel Corporation, known for manufacturing radiation-tolerant and
   radiation-hardened FPGA parts based on its antifuse technology.  We
   have designed a field-programmable analog array test chip which has
   been fabricated in the same technology as Actel's RT-SX line of
   radiation-tolerant chips.  This fabrication process is a 0.22 micron,
   three-metal process optimized for digital circuitry.  The metal-to-metal
   antifuses, when programmed, typically achieve resistances of 20 Ohms or
   lower.  The low resistance of interconnects allows us to reduce the
   granularity of our basic analog building blocks to individual components:
   capacitors, resistors, amplifiers, and analog switches.  Our test chip
   contains twelve modules, each containing a differential amplifier,
   eight programmable capacitors, four programmable resistors, 64 CMOS
   switches, and internal and inter-module routing resources.

   We will report on the measured performance of the test chip, particularly
   as relates to the difficult problem of constructing high-performance
   analog circuits in a substantially digital fabrication process.  Of
   particular concern are the linearity of the capacitors, component
   matching, and performance of a test suite of basic circuit configurations
   including a charge shaping chain, ADC, and filters.  Additionally, we
   will report on the steps we believe are necessary to make the next
   generation design a commercially viable product.