Timing analysis of all signals must be performed. In general, the signals fall into two classes. First, signals such as data, enables, and synchronous inputs must meet setup (tSU) and hold (tH) times. Clock signals must meet width (tW) requirements. These are well-defined and commonly used and will not be discussed further in this application note.
A common mistake in the analysis of digital systems is the timing analysis of asynchronous signals. With respect to flip-flops, these inputs are usually called PRESET and CLEAR. For MSI devices, there are other signals that are similar such as the JAM input to counters or shift registers. Although these signals are labeled "asynchronous" they do have restrictions on their use. Failure to meet the specifications can result in incorrect operation.
The first specification that these signals must meet is minimum pulse width. This is rather straightforward. If this specification is not met, the signal may be ignored or the flip-flop may be driven into a metastable state.
A more subtle requirement, and the one that is commonly missed, is the removal time which is often referred to as tREM. Note that not all manufacturers use this nomenclature; there may be different terms. Essentially, this is the equivalent of a set up time requirement for synchronous inputs. That is, the asynchronous command must be removed at least tREM prior to the next active edge of the clock. As in the case above, if this specification is not met, the signal may be ignored or the flip-flop may be driven into a metastable state.
Lastly, for MSI devices or modules that emulate them, data that is "jammed," as well as any related mode or address inputs, must meet setup and hold times with respect to the asynchronous pulse, similar to that of synchronous signals to the clock.
In summary, some timing requirements of asynchronous inputs of flip-flops are similar to those of clocks; others to those of synchronous data. Specifically, the timing analysis of asynchronous signals must show:
- Proper pulse width of the asynchronous pulse
- Removal of the asynchronous command pulse tREM prior to the next active edge of the clock. This is the equivalent to a setup time requirement.
- Proper asynchronous data setup and hold times with respect to the pulse
Note that not all manufacturers list in their device specification the tREM parameters (or its equivalent). However, all flip-flops do have this requirement; unfortunately not all data sheets specify it. The asynchronous inputs may not be removed asynchronously to the clock for reliable operation.
References and Notes
- "Fundamentals of Testing COS/MOS Circuits," ICAN-6532, J. Flood, RCA Solid State CMOS Integrated Circuits Databook, SSD-250C, 1983.
- Discussion of MetastableStates.
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