“Physical synthesis for Radiation Tolerant FPGAs”

Sanjay Bali
Magma Design Automation

Abstract

As FPGAs become more complex and geometries shrink, it becomes more difficult for traditional synthesis tools to achieve timing closure. The device level timing models used by synthesis tools do not offer the accuracy or the required correlation with backend place and route tools for timing closure. Blast FPGA is the next-generation synthesis solution for high-performance programmable logic devices (PLDs). It features FPGA architecture-specific synthesis and concurrent analysis in a single tool, which provides FPGA designers with higher quality of results (QoR). Unlike traditional FPGA synthesis tools, Blast FPGA delivers highly optimized FPGA implementations and significant performance improvements without manual user interventions, floorplanning or iterations. This is achieved through the physical synthesis technology that considers layout and routing while performing logic synthesis. We will analyze the benefits of the physical synthesis technology to address the needs of improved performance and timing closure on Actel’s radiation tolerant FPGA devices.

 

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