"Performance Optimization in DSP Algorithm to Hardware Transformations"

John Gallagher
Synplicity Inc.

Abstract

DSP designers think of their design performance based on throughput rates.  However, when that design is taken into a logic implementation then what matters most are the clocks. And what impacts clock schemes and overall performance the most are unique aspects of the hardware fabric and the ability to efficiently use low-level resources.  This paper will use the Actel ProASIC architecture as an example of how in going from an algorithmic to a hardware implementation this specific part of the translation process must be understood and carefully optimized to achieve the best performance.  The aim of an automated algorithm to hardware flow is to capture that understanding in heuristics and the optimization into synthesis.  Examples of this include automatically adding extra latency to increase rescheduling effectiveness, and Manual-to-Automatic migration of folding techniques.  A design flow example will show how the Actel Libero Platinum environment provides for these automatic optimizations, as well as the timing analysis capability (SmartTime) to verify improved device performance. 

 

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