"Rapid prototyping of a Hardware Scheduler for Multitasking Acceleration"

Lucien Ngalamou
University of the West Indies, Trinidad and Tobago

Abstract

Many embedded systems use real time operating systems (RTOS) in order to effectively schedule multiple tasks but sequential software logic can create some bottlenecks within the system. Implementing parts of those codes in hardware can increase performance.  We present in this paper a groundwork in developing, testing and implementing a customized Hardware Scheduler IP Core targeting crucial primitives of the popular uC/OS-II RTOS [1].

Our approach uses an FPGA chip as a common integration platform. “ For an SOC chip, the validation of hardware, software, and firmware on a common platform can be accomplished using FPGA-based prototypes [2].” The overall integrated process is shown below.

A significant feature of this study explores the use of the content addressable memory (CAM) technology within the scheduler to reduce the time to insert and remove tasks from the priority list. This is at the heart of the scheduler, as it needs the minimum amount of time to search for a task or to put the tasks in order of ‘priority’ according to the scheduling algorithm used. CAM technology usually allows inserts and deletions in 1 to 2 clock cycles. This CCAM also has the facility for time and event management in hardware, which also contributes, significantly to enhancing performance due to the CCAM structure.

Keywords: hardware Scheduler, FPGA, Rapid Prototyping, and CAM.

References:

  1. Labrosse, Jean J. 1999. MicroC/OS-II. The Real-time Kernel. Kansas, CMP Books.

  2. Mathur, Raj. SOC Prototyping Requirements. [online]. 2004. [cited 10 Feb 2006]. Available from: <http://www.fpgajournal.com/articles/soc_aptix.htm>

2006 MAPLD International Conference Home Page