"A Novel Methodology To Reduce Leakage Power In Master-Slave D Flip-Flops"
Preetham Lakshmikanthan and Adrian Nunez
With miniaturization, power dissipation has become a critical design metric. Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. The subthreshold leakage current increases exponentially in deep-submicron processes and hence is a crucial factor in scaling down designs. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, a novel technique to reduce leakage power in master-slave D flip-flops is presented. Various pull-up network (PUN) and pull-down network (PDN) paths were first identified in the master-slave D flip-flop circuit. Then, sleep-transistor circuitry that achieves cancellation of leakage effects in both the PUN as well as the PDN was applied to all the identified paths. The sleep transistors were a combination of standard voltage threshold (vt) and high-vt devices. A special state-saving dynamic transmission gate latch was designed for retaining data in the D flip-flop during the power-down (sleep) mode. The sleep-embedded master-slave D flip-flops are finally characterized as part of an ultra-low power standard cell library. Significant leakage power savings (average of 18X at a temperature of 27 Deg C) are seen in D flip-flops employing this sleep circuitry when compared to standard D flip-flops. Experimental results show that our technique has an average of 3.01X leakage improvement over the traditional power-gating methodology.
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