"A Performance-Driven Partitioning Algorithm for Hardware/Software Co-Design on FPGA"

Xinming Huang, Cao Liang and Jing Ma
University of New Orleans

Abstract

This paper presents a performance-driven partitioning algorithm that partitions an application into customized hardware and embedded software modules on a single FPGA. While traditional design space exploration algorithms focuses on area and timing delay estimations on different RTL architectures, this paper takes a different approach. A unique partitioning algorithm is developed based on the performance data and block utilization statistics obtained from high-level simulations. For any given application, it first evaluates the base performance by implementing the entire system on an embedded processor. Followed by a course-grain block separation, the run-time execution time and statistics for each block is then obtained individually. The blocks that are frequently used or critical to the throughput of the system are considered for customized hardware implementations. The speedup factors can be evaluated for different hardware/software partitioning candidates, in conjunction with a simple frequency and area utilization model. For a given FPGA device with available resource, the optimal partition result is chosen providing the best performance of the system. As an experimental study, we consider a single-FPGA co-design implementation of MIMO sphere decoder for wireless communications. The decoding algorithm is partitioned into customized hardware and MicroBlaze software modules on a Xilinx FPGA. High-level simulations are used to estimate the performance gains and resource utilization for different partitioning candidates. The final partitioning decision is made based on the run-time performance estimation and specific FGPA resource constrains. The procedure of the partitioning algorithm and the performance evaluation method are discussed in detail. The experimental study demonstrates a maximum speedup of 29 times with only 10% area estimation error for the MIMO decoder design.     

 

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