"Development of Radiation-Hard 32-bit Forth Microprocessor with 0.18 um CMOS Technology"

Edvin Hjortland1, Li Chen1, and Umesh Patel2

1South Dakota School of Mine and Technology
2NASA GSFC

Abstract

A 32-bit configurable radiation-hardened Forth processor is developed and implemented with a 0.18 um CMOS technology. This Forth processor architecture provides high speed and high volume processing capability required for synthetic-aperture radar (SAR) signal processing. This processor uses an RISC-like instruction set with only 29 machine instructions. It has two stacks: the Parameter Stack and the Return Stack which are 256 levels deep. There are 31 primitive words created from 29 machine instructions. The 32-bit Forth processor is designed in VHDL. It is synthesized with a radiation-hard-by-design digital library provided by ATK Mission Research. The fabricated chip will be tested to verify its functional and radiation performance.

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