"Reducing Power Consumption of Radiation Mitigated Designs for FPGAs"

Li Wang1, Matthew French 1, Michael Wirthlin 2, Paul Graham3 

1University of Southern California, Information Sciences Institute
Brigham Young University
Los Alamos National Laboratory


We consider design automation for evaluating and improving the reliability and power optimization of field-programmable-gate-array (FPGA) designs for space applications. We develop a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using FPGA technology. SRAM-based FPGAs are sensitive to SEUs due to the large amount of static memory within them. Many techniques have been proposed to address the vulnerabilities of SRAM-based FPGA architecture. However all the techniques require extra hardware overhead, and thus more power. Therefore, power has become a critical issue for space-based platforms. The existing COTS power tools provide limited utility to minimize power. This paper is focused on power optimization and its impact on reliability using the developed FPGA Low-Power Intelligent Tool Environment (LITE) and partial TMR. A benchmark and its radiation-mitigated designs are applied with the LITE tool, and the power improvement and reliability results are discussed.  

In the first section, we introduce the low-power tool environment and its power optimization techniques. The LITE tool infrastructure is extended from JHDL environment and EDIF import tools developed by BYU. The JHDL and EDIF import tools allow querying circuit components, running simulations, and tracking signal transitions. Built upon these capabilities, LITE added power features to enable power modeling, visualizing instantaneous and average power consumption over time, spotting power intensive modules, and facilitating power optimization. The power techniques in LITE is implemented to address Xilinx tool flows. The techniques do not modify design logic, but rather create constraints to assist the Xilinx tools to place and route designs in power-favored way while user's throughput specifications are still satisfied.

The second section introduces the benchmark that is used to evaluate the power optimization algorithms. It is a highly pipelined image convolution engine that enables to process three input data in parallel and create one output each clock cycle. The design is implemented in Xilinx Virtex-II-1000 FPGA, and it utilizes nine multipliers and three block RAMs. Triple Modular Redundancy (TMR) is applied to the image convolution design using the BYU-LANL TMR (BLTMR) tool. BLTMR is a partial TMR tool that targets reducing the TMR hardware overhead by applying mitigation selectively on designs. Two versions of BLTMR’ed designs are created. In the first design, only the structures that cause “persistent” errors are triplicated. In this case, about 35% of the original instances are TMR’ed. The second design is a full TMR version. The BLTMR'ed designs as well as the original design go through the LITE tool flow to achieve the power optimization constraints. Xilinx ISE and XPower are used to obtain the power consumption data.

In the next section of the paper we present the power testing results of the benchmark. Five power minimization techniques and their combinations are applied to the imagine convolution kernel. Eight sets of random tap values are utilized to each circuit (TMR'ed or non-TMR'ed). Power is improved by 8.4% on the non-TMR'ed design. The partial and full BLTMR'ed designs have power reduction of 9.0% and 14.2% respectively. The power optimized designs are tested for radiation sensitivity with the SEU-emulator developed by LANL. The results show that the designs present identical radiation mitigation capability after the power optimization is applied.

Conclusions are offered in the final section in this paper. A FPGA Low-power Intelligent Tool Environment is presented, and an image convolution kernel is performed with the power optimization techniques using the LITE tool. The results show that power improvement on both the original design and the radiation mitigated designs are possible with little trade-off in reliability.


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