"Towards SEU-Tolerance on FPGA-Based Avionics: A Tale of Two Implementations"

Yutao He, Mandy Wang, Ryan Stern, and Gary Bolotin
Jet Propulsion Laboratory

Abstract

This paper presents design and implementation of the SEU mitigation technology, smCore, for avionics systems based upon the Xilinx Virtex II Pro FPGA. The goal is to cover all the areas of susceptibility within the Virtex II Pro FPGA device and to provide a complete, modular, pluggable, and reusable SEU mitigation solution for various applications with different SEU tolerance requirements in low to moderate radiation environments. smCore consists of a set of individual IP cores that provides detection, correction, recovery, and notification capabilities and that can be easily inserted into design of FPGA-based avionics via the CAD-tool-enabled design flow. The first element of smCore that is aimed at 100% detection and containment of SEU-induced errors for non-time-critical space applications has been implemented as proof-of-concept using two different generations of Xilinx provided CAD tool: V2PDK and EDK. Results from these implementations are summarized and reported.

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