"Enhanced Fault Tolerance for On Board FPGA Based Reconfigurable Computing"

Grant L. Smith
Honeywell Inc.

Abstract

Reconfigurable computing architectures based on Field Programmable Gate Arrays (FPGAs) offer significant performance improvements over traditional on-board processing solutions. The application of commercial-off-the-shelf (COTS) FPGA processing components requires radiation-effect detection and mitigation strategy to compensate for the FPGAs' susceptibility to single event upsets (SEUs), single event functional interrupts (SEFIs) and single event transient (SET) effects. A reconfigurable computing architecture that uses external triple modular redundancy (TMR) via a radiation-hardened ASIC provides the most robust approach to SEU, SEFI and SET detection and mitigation. Honeywell has designed a TMR Voter ASIC with an integrated FPGA configuration manager that can automatically reconfigure an upset FPGA upon TMR error detection. The automatic configuration manager also has features to filter out SET effects and resynchronization of the effected FPGA with the remaining two FPGAs operating in a self checking pair (SCP) mode. Filtering transient events and minimizing reconfiguration and resynchronization times enables high performance FPGA-based processors to provide high system availability with minimal software/system controller intervention.

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