"A High-Level Development Framework for Run-Time Reconfigurable Applications"

Stephen Craven and Peter Athanas
Virginia Polytechnic Institute and State University


There is a growing interest from the reconfigurable computing community in two distinct technologies, high-level synthesis and Run-Time Reconfiguration (RTR).  Several companies currently market successful high-level language-to-gates compilers [1] that significantly reduce hardware development time.  FPGA vendors, awakened to the benefits of RTR by the trend towards software defined radio, now sell devices with configuration architectures more amenable to dynamic reconfiguration [2] and are in the process of providing implementation tool support that has long hindered RTR usability [3,4].

Capitalizing on these trends, we have defined an RTR development framework for streaming applications consisting of a high-level design environment and implementation flow that significantly reduces the effort required to field RTR designs.  Unlike previous RTR development frameworks, our work unifies hardware and embedded software development and supports partial reconfiguration, automatically generating an internal configuration controller.

While the framework itself is architecture-agnostic, we are integrating a high-level design environment, Impulse Accelerated Technologies’ Impulse C, with an automated implementation flow targeting Xilinx FPGAs.  Impulse C, a C-to-gates development environment utilizing the communicating sequential processes computational model, is being extended to permit the simulation and synthesis of RTR applications from a high-level C specification.

Well-suited for signal processing, networking, or cryptography applications, this framework is being used to implement an encryption engine featuring dynamically swappable cores.  The final paper will present our results along with our impressions of high level synthesis and vendor RTR support.


  1. B. Holland, M. Vacas, V. Aggarwal, R. DeVille, I. Troxel, and A. George, “Survey of C-based Application Mapping Tools for Reconfigurable Computing,” Proceedings of the 8th Annual Conference on Military and Aerospace Programmable Logic Devices, MAPLD 2005, Washington, DC, Sep 2005. 

  2. Xilinx, “Xilinx UG071 Virtex-4 Configuration Guide,” available for download at: www.xilinx.com/bvdocs/userguides/ug071.pdf 

  3. D. McGrath, “FPGA TOOLS: PlanAhead redefines hierarchical design reconfiguration,” EETimes, February 6, 2006. 

  4. S. Lass, “RE: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs,” comp.arch.fpga newsgroup, March 6, 2006, available for download at:http://groups.google.com/group/comp.arch.fpga/msg/d418a230db16301a


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