"FPGA-Based Laser Beam Steering System"
Brian L. Snyder
Goodrich Corporation Advanced Sensors Technical Center
Motor- and mirror-based laser scanning systems tend to be bulky, noisy, and suffer from low reliability due to the relatively high content of moving parts. In addition, considerable processing power is needed to correct the returned signal for the delay in the system from the firing of the laser to the reception of the return signal, and to compensate for various positioning errors inherent in a mechanical system. System accuracy and reliability can both be improved if the moving parts can be minimized, or even eliminated altogether.
This paper describes a novel FPGA-based beam-steering system developed by the Goodrich Advanced Sensors Technical Center. In place of motors and mirrors, this system uses a pair of diffractive phased array gratings, driven by piezoelectric actuators, to steer a laser beam in two dimensions. The feature size of the grating allows for deflection of the beam by ± 20º or more in any direction, with total movement by the gratings of only a few hundred microns. In this system, the laser can be aimed at any point in space (within the limits of the grating deflection) or it can be scanned in a modified raster-scan fashion. Furthermore, the area to be scanned can be selected by the user to cover as large or small an area as desired. The FPGA tracks the laser aim point via optical encoders on the grating frames, determines when the laser should be fired (based on user designated parameters), and writes motion-control data to a dual D/A converter to adjust laser position based on system motion control algorithms. Since the FPGA knows the precise location of the laser at all times, the noise and errors inherent in motor-and-mirror systems is eliminated. Finally, the FPGA contains various I/O interfaces for system communication. A SPI interface is implemented for communication with the system display circuitry, and an RS232 interface is implemented to communicate with an outside host computer for test purposes.
The system prototype is implemented in a Xilinx Virtex4 FPGA. The algorithm processing for the prototype uses a Texas Instruments’ DSP, but future enhancements will implement the control algorithms directly in the FPGA fabric, eliminating the need for an external processor.
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