"Unified System Verification Using a VHPI Abstraction Layer"

Petersen F. Curt1, Daniel K. Price2, Michael R. Bodnar2, and James P. Durbano1

1EM Photonics, Inc.
2University of Delaware


The leap from simulation to platform verification is not an easy one.  Hardware simulation requires an HDL testbench that carefully monitors cycle-accurate timing, while platform verification requires a software test program that interfaces with the platform’s device driver.  A typical development cycle incorporating these elements consists of the following steps: 

  1. Write HDL to describe the system

  2. Simulate HDL, verifying against an HDL testbench

  3. Synthesize the HDL and implement on hardware

  4. Verify the hardware with a software test program

The largest disadvantage of this process is the need to maintain two separate interfaces to the system:  one using HDL and the other using a software test program.  The HDL interface is used to implement and verify the logic operations of the design.  Once verified, the design can be implemented in physical hardware.  However, a C++ test program is still required to preprocess the data before it is sent to hardware.  This reliance on both HDL and C++ platforms, which perform many of the same operations, results in a duplicated effort and twice as much code in which bugs can be introduced.  In response to this, we created a common simulation wrapper to allow easy migration from simulation to platform verification.

This paper presents an improved approach to the task of verification.  We propose a unified verification suite that utilizes a hardware abstraction layer to interface between high-level platform verification code, and either of the two target environments (HDL simulation or real hardware), thus eliminating the need for multiple versions of test code.  The key to this method is the design of a new hardware abstraction layer (HAL) (Figure 1).  This layer provides seamless integration between the C++ test program and either the HDL simulator or the physical hardware.

Figure 1. Unified Verification A hardware abstraction layer interfaces between a uniform C++ test program and two verification environments.

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