"Layout Guidelines to Minimize Latchup in CMOS Circuits using Guard Rings"

Pamela Obiomon
Prairie View A&M University

Abstract

This paper provides guidelines for selecting, implementing and testing guard structures.  To provide these guidelines structural differences of existing guard rings and guard diffusions have been explored and the influence of the guard structure layout on CMOS latchup has been investigated. There are only two types of guard structures, majority carrier and minority carrier, but there are numerous ways of implementing them to minimize latchup under certain conditions.  Majority and minority carrier guard structures can be located in the substrate a) near the emitting source, b) surrounding the emitter, c) near the well edge, d) surrounding the well edge or, e) in various positions inside the well.  In order to prevent latchup using guard structures, a chip designer must select a type of guard structure.  In addition to selecting the appropriate type of guard structure, decisions must be made to select an appropriate location and an appropriate guard ring width for a particular application. The rules for using guard structures are far from universal and determining which guard structure to implement can be a difficult task for a less experienced designer. The guidelines presented in this paper will assist a less experienced designer in making decisions as to which guard structure to select, where to locate the structure within a CMOS layout and how to test the efficiency of the guarded structure. 

2006 MAPLD International Conference Home Page