“FPGA Core Implementation of Space Data Buses Interfaces”
M. Prieto, A. Eguidazu, V. Lopez, S. Sanchez, O.R. Polo, I.G. Tejedor and D. Meziat
University of Alcala
This paper presents the current VHDL core developments of the Space Research Group of the University of Alcala. Our two main development lines on FPGA are the peripheral interfacing through the main standard data buses, and the system-on-chip technology. Our aim is to have a library of fully validated interface cores, in order to adapt our designs to the requirements of a specific project, increasing the flexibility and reducing costs and development time. This library package is composed of four cores: MIL-STD-1553B, SpaceWire, CAN-BUS and TTC-B01 ESA standard. In this sense, we have developed a synthesizable MIL-STD-1553B remote terminal core and a SpaceWire interface core. An overview of these cores and their validation plan and results are presented. As an application example, we are currently depeveloping a SoC based on an 8051 microcontroller with CAN-BUS interface. Our goal is to obtain a fault-tolerant 8051-SoC to be integrated as a Stand-Alone remote terminal controller for payload interface with OBDH. The SoC hardware and software design is presented.
Key-words: FPGA cores, MIL-STD-1553, Spacewire, System-On-Chip
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