"Lessons Learned from Employing Rapid Development Design Techniques"

Edward R. Oates, John P. Johnston and Bruce Reidenbach
ITT Aerospace

Abstract

Rapid development techniques employed in the design of an Actel FPGA based flight experiment control and data processing application successfully reduced program schedule along with risks. Use of these techniques allowed the iterative hardware and firmware design process to proceed incrementally in parallel with maturing of the processing and control functional requirements. These techniques integrated well with the development results from MATLAB based processing models and eased the verification of internal functional processes as well as external interfaces and functional operations. This paper takes a look at the techniques that proved valuable during design implementation, test and verification:

        A flight-like prototype FPGA module was designed early in the program that made use of sockets for mounting the anti-fuse Actel FPGAs as successive development iterations were released for checkout and verification.  This allowed rapid development and checkout of module functional requirements prior to final design & build of flight modules, as well as supporting special test equipment.  It also promoted early detection of unforeseen problems as well as creative and rapid cures to unforeseen internal design issues as they arose and external system integration problems identified late in the program. 

        A MATLAB-based model developed to define the processing requirements for instantiation in the module FPGAs also served to develop incoming test data sets and output verification data sets, as well as define module test software performance requirements.

        Portions of the firmware were hosted on purchased Virtex-based Memec cards that served not only as a test bench to verify early instantiations of processing algorithms, but also as the core of supporting test equipment.  Specifically, the core served as a Functional Simulator that was used to verify system interface control & telemetry functions early in the program; and a portable module test system capable of limited verification of all module functions and interfaces at the system site.

 

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