"Improving FPGA Yield with Defect Tolerance"

Asbjoern Djupdal and Pauline C Haddow
The Norwegian University of Science and Technology

Abstract

As technology scales, the problem of production defects is expected to increase. This makes maintaining device yield a challenge. Also, it may be expected that more and more defect circuits will pass the production tests as the device testing problem will increase.

Architectural solutions like redundancy could be used to tolerate defects that would otherwise result in erroneous operation. Triple Modular Redundancy (TMR) is a well known fault tolerance technique with the unfortunate side-effect of tripled area and increased power consumption. To avoid reducing the total number of usable dies from a wafer (effective yield), area efficient defect tolerance techniques are, therefore, needed.

Reconfigurable technology has become more and more popular in recent years. However, like ASIC design, reconfigurable technology also suffers from production defects. However, unlike ASIC design, reconfigurable technology provides a bridge between production and the application designer. The inclusion of defect tolerance in the FPGA architecture would provide a functionally correct FPGA for the application designer, despite production defects. As such, the application designer is relieved of the extra complexity of designing for imperfect devices.

This paper presents a survey of known approaches to making defect tolerant FPGAs and discusses their advantages and disadvantages, especially in the context of maintaining FPGA yield and device correctness.

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