"SEFI Mitigation for Commercial Microprocessors in Space-Proton Testing Demonstration, SBC Integration and ASIC Development"

David R. Czajkowski, Murat Goksel, Manish Pagey, and David J. Strobel
Space Micro Inc.

Abstract

The use of leading-edge commercial microprocessors in space applications is often precluded due to their susceptibility to single-event upsets (SEU) and single-event functional interrupts (SEFI). The SEU and SEFI threshold LETs for commercial microprocessors can range from 0.2 to 9 MeV-cm2/mg [irom2000tns]. In orbit environments, these thresholds translate to upset rates ranging from a few upsets per day (unacceptable) to a single upset per year (acceptable).

SEFIs are observed in complex integrated circuits and microprocessors as unexpected “hangs” during normal operation of the component. Such interruptions are believed to be due to single-event upsets in critical regions (such as a state machine) that force the circuit to an invalid state. Swift et al. [Swift2001tns] have advised space designers that SEFI is an emerging radiation hardness assurance issue with the solution cited as “removal of power supply and subsequent re-initialization.” This is currently the most common method of recovering from SEFI events in microprocessors. While a very safe solution, this procedure can be time consuming and result in severe design and operational consequences.

The mitigation technique presented in this paper uses an external circuit, called the “SEFI Hardened Core” (H-Core), to monitor and manage a COTS microprocessor (CPU) during SEFI events. The H-Core is responsible for detecting the occurrence of SEFI events and, in case of such an event, asserting a sequence of signals until complete recovery of the microprocessor is confirmed. In addition, the H-Core also provides capabilities for application programs to restore their states after recovery from a SEFI event.

Demonstration of SEFI recovery technology is presented for two advanced COTS microprocessors, based on proton testing (51 and 63 Mev) at the UC Davis cyclotron facility. Integration of H-core within Space Micro's Proton series space rad hard SBC family will be described.

The development of an ASIC to implement this function is also described with initial test results from Peregrine Semiconductor wafer foundry. The H-core device is now available in a rad hard Actel FPGA, and will be available in 1Q2007 in a radiation hardened ASIC from Space Micro.

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