"A Rollback Recovery System for Embedded FPGA Processors"
J. Reed Walker and Chris Papachristou
Case Western Reserve University
This work investigates the use of rollback recovery as it applies to an embedded processor system in the context of field-programmable gate arrays (FPGA). An interrupt-based strategy was developed, in which processor registers were recovered using software routines and active data memory was recovered using parallel direct memory access (DMA) transfers. The rollback system was implemented on a platform FPGA, Xilinx Virtex-II Pro with embedded PowerPC processor. Rollback of program execution, data structures, operating system threads, and I/O sequences was demonstrated. With checkpointing performance at 95%, the mean recovery time was observed as ~10,000 cycles for rollback of processor registers and ~300,000 cycles for rollback of active data memory. These results demonstrate a significant improvement over full system restart, which typically incurs much longer recovery times.
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