"Effective Use of Global Clock Networks in Actel RTAX-S Devices"
Amal Zerrouki and Nizar Abdallah
With their recent architectural evolutions and ever-increasing capacity, FPGAs are now more than ever closer to delivering ASIC-like density and performance. There is however a particular set of challenges when developing an FPGA-based system, due mainly to its predefined structure. Designers need to figure out how to get the most out of FPGA resources. Although EDA tools help in that regard, a manual intervention from designers is often required to get the last drop of performance out of the architecture.
This paper focuses on an important FPGA feature of the Actel RTAX-S family: Global resources or clocks. This feature is essential in helping designers meet timing and power requirements. After a short architecture description, we go into more details over the timing characteristics and particularly the controlled variability and low-skew capability it provides. This is followed by tips for skew minimization and canceling through placement constraints. Finally, we also look at the power aspect and provide power-aware placement recommendations that highlight the flexibility and ease-of-use of this feature.
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