"EMD: An Enhanced Min-Delay Calculation for a Reliable Timing Analysis with Actel FPGAs"
Nizar Abdallah, Denis Hommais, and Amal Zerrouki
Static timing analysis (STA) is instrumental in verifying the timing behavior of digital designs. Maximum (resp. minimum) data path delays are used to check for setup (resp. hold) violations. In older, slower generations of FPGA devices, the hold check was a second order concern with data path delays often slow enough to be bigger than the clock skew or the chip-to-chip minimum delay requirements. Timing parameters used for cell and net delays reflected this fact by being worst-case delays mainly focusing on providing a conservative setup analysis. Minimum delay calculation only accounted for variation in process, voltage, and temperature but not for contextual variations. This is no longer sustainable in today’s FPGA technologies where cycle times have been dramatically shrinking, driven both by faster gates and by more aggressive designs with fewer logic levels per cycle. It is expected that clock skew, as a fraction of cycle time will keep on increasing, requiring careful minimum delay calculation and hold verification, especially for mission critical designs. The problem is even more exacerbated in deep submicron technologies due to an increasing number of contextual delay variation factors such as crosstalk noise. This paper examines the main sources of delay variability and proposes a practical characterization-based methodology to estimate minimum delays in FPGA devices for a comprehensive within-chip and chip-to-chip hold verification.
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