"Design Considerations for Implementing Triple Module Redundancy in Xilinx FPGAs"

Chen Wei Tseng1, Greg Miller1, Carl Carmichael1, Gary Swift2, and Jeffrey George3

1Xilinx
2JPL/Caltech
3Aerospace Corp.

Abstract

The use of Xilinx FPGAs in space applications has afforded designers with many benefits ranging from shorter design cycles and design flexibility such as post integration design modification, to ease of implementation, testing and debugging application algorithms. However, designing FPGAs with proper mitigation schemes incorporated within a standard design flow requires look ahead planning for hardware and code implementation. This paper will focus on selected considerations for implementing FPGA designs in space applications.  

This paper will highlight methods for more robust design implementations and overcoming typical challenges for triple modular redundancy. Topics of consideration will include: Finite State-Machine encoding schemes; Asynchronous data transfers across clock domains; and choosing IO mitigation schemes interface protocols such as PCI and Spacewire which require the use of bidirectional IO and high speed transceivers. 

Additionally, the integration of FPGA design (TMR) and FPGA management (Scrubbing) will be examined as well as the implementation of TMR on high level architectural blocks such as Block Memory Arrays, Digital Clock Managers and embedded RAM elements.

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