"SEU Error Detection and Correction Techniques for the Xilinx Virtex-4 FPGA"

Chen Wei Tseng1, Carl Carmichael1, Gary Swift2, and Jeffrey George3

1Xilinx
2JPL/Caltech
3Aerospace Corp.

Abstract

The Xilinx Virtex-4TM FPGA is incorporated with an entirely new configuration architecture completely unlike that of the other Virtex series predecessors. The Virtex-4 configuration architecture has new feature enhancements such as embedded error detection modules, LUT isolation for enhanced embedded computing applications, and a new memory frame addressing topology for advanced reconfigurable computing applications. 

IP Algorithms have been developed for the Single Event Effects Testing as well as flight integration of the Virtex-4 FPGA. This paper will focus on configuration architecture of all three Virtex-4 families (LX, SX, and FX), the significant differences of scrubbing and readback techniques between the Virtex-4 and the Virtex-2 FPGAs, and will also discuss the benefits of the new Virtex-4 family from a TMRTool and Designer’s point of view regarding the usage of device primitives ( Half-Latches, LUTRAM, and SRL16) and their impact on the use of high level function cores. Additionally, the resukts of Heavy Ion testing will be presented for the static and dynamic SEU response for the configuration and Block Memory storage cells as well as Single Event Functional Interrupts.

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