"Matrix Algorithm Cores Generator on Reconfigurable Hardware for Image Processing"

A. Amira, F. Bensaali, I.S. Uzun and A. Ahmed Said
Brunel University


The nature of some space applications dealing with image visualization, analysis and processing involve performing complex tasks repeatedly on a large set of image data, often under real-time requirements. Therefore, high performance systems are required by the developers for fast computations.Many researchers have begun to recognize the potential of reconfigurable hardware such as filed-programable gate arrays in accelerating such computationally intensive applications. A close examination of the algorithms used in these, and related, applications reveals that many of the fundamental actions involve matrix algorithms.

In this paper, a system for matrix algorithm cores generation is described. The system provides a catalog of efficient user-customisable cores, designed for filed-programable gate arrays implementation, ranging in three different matrix algorithm categories: (i) matrix operations, (ii) matrix transforms and (iii) matrix decomposition. The generated core can be either a general purpose or a specific application core. The methodology used in the design and implementation of three specific image processing application cores is presented. The first core is a fully pipelined matrix multiplier for colour space conversion based on distributed arithmetic principles, the second core is an efficient discrete wavelet transform used in video compression, while the third one is a systolic singular value decomposition designed for image denoising. The implementation of these cores has been carried out using a hybrid design approach based on Celoxica Handel-C which is used as a wrapper for highly optimized VHDL cores. Maximum optimization of performance metrics has been achieved by careful manual floor planning of the design, with particular attention paid to the critical paths and pin assignment. The algorithms have been implemented and verified on the RC1000 board equipped with the Xilinx Virtex-2000E FPGA.

Keywords: Matrix algorithms, field programmable gate array, image processing, colour space conversion, discrete wavelet transform, singular value decomposition, Handel C, Virtex


2006 MAPLD International Conference Home Page