"In-System Test for FPGAs"

Dan Gardner1, Ron Press1, and Melanie Berg2

1Mentor Graphics
2NASA GSFC/Muniz Technologies

Abstract

A design for a one-time programmable (OTP) FPGA device in a space environment will employ many radiation risk mitigation techniques from finite state machine (FSM) design to triple-module redundancy (TMR). Up to this point, few designs have used design-for-test (DFT) techniques with a FPGA to validate that a device’s programming is not upset or damaged.  These techniques are especially important for OTP devices, since the programming cannot simply be scrubbed. 

Scan test was introduced to the industry to enable high quality automated test pattern generation.  Initially, it was focused on detecting defective devices from a production line and avoiding shipping them to customers.  However, the great deal of control and observability within a device available through the scan logic presents many other opportunities.  Scan test usage has recently expanded to failure diagnosis and defect localization in embedded systems. 

This paper discusses the ease of adding DFT flows to an existing FPGA methodology to allow at speed testing, even when the system is deployed in a remote location.  A case study is included of a design for an Actel RTAX-S design created by Melanie Berg to show the overall impact on area and performance when inserting the scan logic.  In general, scan insertion adds an additional MUX in front of each register.  In most cases, this MUX can be absorbed into the R-Cell, so it will not effect the combinatorial area utilization.  In early testing, the combinatorial cell usage grows less than 20% on average, quite a bit smaller impact than the 3x area increase seen with TMR.  The effect on performance was legible as timing remained approximately the same.  Another positive sign is that early testing under the beam showed the cross section added by the scan insertion logic was minimal so there were negligible differences in radiation effects before and after scan insertion. 

So far, FPGA designers do not have much experience with these techniques, so the applications are likely to expand well beyond what the authors have considered up to this point.  DFT techniques are typically netlist operations, so scan insertion and built in self test tools are often easily ported to new technologies, like FPGA.

 

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