"Reliability Update on the Aeroflex ViaLink FPGA"

Ronald Lake
Aeroflex Colorado Springs


Aeroflex Colorado Springs will update the status of testing on the ViaLinkä based RadHard Eclipse FPGA. Cumulative results from HTOL / LTOL reliability analysis will be presented along with results for testing simultaneously switching outputs and power sequencing. Multiple wafer lots are currently undergoing life test, and the latest result for each test lot will be presented.  

For each test, Aeroflex will review both the design and the test techniques used to obtain data. Two designs will be discussed. The first design, for reliability analysis, has undergone a series of modifications to improve the ability to look at both long and short delay chains. Multiple timing taps have been inserted into each delay path to improve the resolution of analyzing delay path changes. This reliability design will also be used to perform the power sequencing analysis.  

The second design, for simultaneously switching output analysis, is used to create worst case noise to analyze the effect of ground bounce on the RadHard Eclipse FPGA. The Teradyne Tiger tester is used to define multiple loading and grounding conditions for this test. Both normal and fast slew rate output buffers are analyzed in this test.

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