“Robust FPGA/Embedded-Processor Design: Design Flow for SEU Mitigation”
Gregory Miller and Carl Carmichael, Xilinx Corp.
Gary Swift and Steven Guertin, JPL/Caltech
New generation FPGAs with embedded processors offer unprecedented power to address complex mil/aero functionality needs. However, making sense of the hardware/software and mitigation process can be complex and time consuming. The engineer must take into account proper design flow and tool practices that can properly mitigate a single embedded processor in an FPGA. Software can also be an issue with the initialization of executable code and proper handling of code execution.
Focusing on the Xilinx XQR2VP40 FPGA, this talk will take an example spacecraft application and will show the proper design flow from system creation to a fully mitigated support system around the single processor. We'll show how to proceed using available design tools to help with appropriate resource utilization, in particular the ISE and TMRTool for the hardware side and EDK for the software side. We will conclude with a few guiding principles.
2006 MAPLD International Conference Home Page