"High Performance SEU Mitigation for the Digital Channelizer Unit – Lessons Learned"

Jonathan F. Feifarek and Timothy C. Gallagher
Lockheed Martin Space Systems Company

Abstract

As FPGAs are used in an increasing number of complex high throughput, data processing intensive space applications, the need for a variety of Single Event Upset (SEU) mitigation techniques has also increased. Modern systems contain multiple FPGAs which drive the optimization and trade-off of differing design parameters to an extent that a viable SEU strategy is design-specific, employing a number of local mitigation “tactics”.

This paper presents the mitigation techniques explored and utilized for the Digital Channelizer Unit which is a digital communications and switching system employing 38 FPGAs comprised of 15 RAM based and 23 Antifuse based devices. We present techniques available to the designer, including ones incorporated by the authors in previous applications, then identify the design parameter advantages and disadvantages of each. Particular emphasis is placed on meeting commercial customer's "availability" requirements.

2006 MAPLD International Conference Home Page