"Particle Test of Xilinx Virtex-II FPGA using XTMR Mitigation Technique"
Fredrik Sturesson1, Stanley Mattsson and Reno Harboe-Sorensen2
1Saab Ericsson Space AB
This report presents the results from heavy ion testing of Xilinx Virtex-II FPGA using Triple Modular Redundancy mitigation with Xilinx XTMR tool. The tests have been performed on specific and application like designs with continuous correction of upsets in configuration data. All tests have been performed on a XQR2V3000 in a 676-pin plastic package.
Flux dependent errors are a well known phenomenon when testing SRAM based FPGAs in accelerator environment. The probability for more than one particle to give more upsets in the FPGA than the mitigation can handle causes these flux dependent errors.
This fact makes it complicated to reveal other the errors mechanism that could be dominant in a space environment.
A specific test design has been developed to minimize these effects. This design has been compared with an application like design and one without mitigation.
Output errors from the user-logic have been recorded in parallel with recording of upsets in the configuration bits. The recorded error rates have been compared to the configuration bit upset rates in each test run. The error rates fits well to the probability function for multi particle upsets overcoming the mitigation scheme. With the specific test design we have minimized these effects.
Tests have been performed from a LET value of 1.8 to 60 MeV/mg/cm2. With a particle flux that in average give about 3 concurrent configuration bit upsets in the DUT, the saturation error cross section has been recorded to 4E-4 cm2/device. In a deeper analysis of the error data it can be concluded that a major part of all recorded errors must originate from multi particle upsets overcoming the mitigation scheme. The conclusion is that the saturation error cross section in space environment would be below 4E-4 cm2/device. How much is impossible to say.
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