"Fault Tolerant H.264 Decoder Implemented on a Reconfigurable Instruction Cell Architecture"

Adam Major, Mark Milward, Sami Khawam, Ioannis Nousias, Ying Yi and Tughrul Arslan
University of Edinburgh


Interest in reconfigurable architectures is increasing rapidly due to their ability to combine immense flexibility and performance with relatively low development and support costs. ASIC designs are expensive to develop, both in terms of economic outlay and time consumption; and they cannot be modified trivially post-fabrication. Conversely, reconfigurable devices can be updated to support new and evolving standards through a simple series of software updates. Reduced costs and faster time to market translates into far lower risk factors for new developments.

The advantages afforded by these systems make them obvious candidates for the implementation of future imaging and video applications such as the recently introduced Joint Video Team (JVT) standard h.264[1]. This standard is able to achieve a 50% bit rate reduction over previous standards MPEG-2 and h.263 [2] at the expense of greatly increased computational complexity [3].

Reconfigurable technologies also present designers with new options for fault tolerant design. For devices which are to be deployed in system critical applications or in environments containing high levels of ionising radiation, fault tolerance is of utmost importance. Bombardment by charged particles from sources such as solar and cosmic rays can lead to ionisation damage as charged particles pass through a system’s logical elements leaving a behind trail of electron hole pairs [4]. The effects of such collisions are varied. A particle could simply induce current fluctuations causing temporary computational errors. However, it could also cause the permanent alteration of a transistor’s characteristics or even overload and destroy it. Designs such as that presented in [5] can continue to operate effectively even after localised failures by dynamically re-deploying around damaged silicon.

However, current reconfigurable systems are generally FPGA or SoC based and consequently consume high levels of both power and area due to the interconnect and switching structures required to route between Combinational Logic Blocks [6]. The Reconfigurable Instruction Cell Architecture (RICA) has recently emerged as a microcontroller sized, ultra low power, high performance, ANSI-C programmable embedded core which aims to provide a solution to the requirements of future system critical mobile applications [7]. This paper presents a new Baseline Profile compliant h.264 decoder implementation on RICA and proposes its configuration for deployment in a system critical scenario operating in an environment high in ionising radiation. The cost of employing a redundancy based radiation hardening scheme to provide the required fault tolerance is assessed in terms of power and area. Results demonstrate that RICA approaches FPGA performance with power figures and area comparable to that of a microcontroller such as ARM.



[1]    Joint Video Team of ITU-T and ISO/IEC JTC 1, “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. h.264 | ISO/IEC 14496-10 AVC),” Joint Video Team (JVT) of  ISO/IEC MPEG and ITU-T VCEG, JVT G050, March 2003.

[2]     Wiegand, T.; Sullivan, G.J.; Bjntegaard, G.; Luthra, A.; “Overview of the H.264/AVC video coding standard”
Circuits and Systems for Video Technology, IEEE Transactions on, Volume 13,  Issue 7,  July 2003 Page(s):560 – 576

[3]     J. Ostermann, J. Bormans, P. List, D. Marpe, M. Narroschke, F. Pereira, T. Stockhammer, T. Wedi, “Viedo coding with H.264/AVC: Tools, Performance, and Complexity”, IEEE Circuits and Systems Magazine, First Quarter 2004, pp.  7-28.

[4]     NASA Scientific and Technical Information, NASA Thesaurus Volume 1- Hierarchical Listing with Definitions, NASA, NASA/SP-2006-7501/VOL1, 2006

[5]     Power Comparison, RapidChip© Platform ASICs vs. FPGAs

[6]     B.I. Hounsell and T. Arslan: “An Embedded Programmable Core for the Implementation of High Performance Digital Filters”, ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International, 12-15 Sept. 2001 Page(s):169 - 174

[7]     Reconfigurable Instruction Cell Array, U.K. Patent Application Number 0508589.9



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