"Radiation-Induced Domain Crossing Events in Xilinx FPGAs"

Heather Quinn1, Paul Graham1, Keith Morgan1, James Moore1, and Jeff George2
Los Alamos National Laboratory
2The Aerospace Corporation


In recent years, field-programmable gate arrays (FPGAs) with volatile programming memory, such as the Xilinx Virtex families, have made inroads into space-based processing tasks. The main challenge of using FPGAs in the space environment is mitigating the effects of radiation-induced single-event upsets (SEUs) within these devices.  These upsets could modify both the data being processed and the function and wiring of the digital circuits themselves.

Several engineers and researchers have demonstrated that logic-level triple-modular redundancy (TMR) with scrubbing of the FPGA's programming (or configuration) data effectively mitigates the results of radiation-induced SEUs. A cross-family comparison of all four Virtex families shows that the single bit event cross-section continues to decrease with each newer family, but that the multi-bit event cross-section increases dramatically with each newer family.  Our testing has shown that only 7.5% of heavy ion events for the Virtex-I family were multi-bit upsets, whereas nearly 50% of heavy ion events for the Virtex-4 family were multi-bit upsets. Our results also show that multi-bit upsets can increase by a factor of five when the radiation events strike the device at an angle. Therefore, radiation-induced domain crossing events, where a single event affects multiple domains, has become more likely.

In this talk, we will present a probability model that predicts the likelihood of domain crossing events for user FPGA designs. This model is based on single-bit and multi-bit fault injection emulation on FPGA designs to determine the domain crossing event cross-section.  This cross-section is then correlated to the expected on-orbit fault rate to determine the probability of a domain crossing event in the deployed design.

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