"Radio Design using Xilinx System Generator"
Xilinx promises quick and easy designs for implementation onto FPGAs using software blocksets that run within the Matlab/SIMULINK environment. This visual design method brings the world of FPGA implementation to the doorstep of the DSP engineer who has no prior FPGA experience. This study demonstrates how easy it is to design and implement radio designs on FPGAs simply by connecting blocks. When paired with RF front ends which can be bought commercial off-the-shelf, the engineer has a complete physical layer testbed in with to try out techniques such as novel synchronization or equalization methods. An 802.11b physical layer receiver design complete with despreader and descrambler will be discussed. A full 2x2 MIMO system will also be reviewed. This “lessons learned” project will concentrate on resampling and pipelining in order to meet timing requirements for the Virtex II based XtremeDSP kits.
2006 MAPLD International Conference Home Page