"Structured ASIC for SEU Mitigation of SRAM-based FPGAs"
Bruce Euzent, Chih-Ching Shih, Cheng Huang, Bill Kwong, Hee Kong Phoon, Kar Keng Chua, and Sammy Cheung
The single event upsets (SEU) for the configuration RAM of SRAM-based FPGAs can be mitigated with cyclic redundancy check (CRC) for error detection and then reprogramming or rebooting the FPGA to fix the error. The system down time for reprogramming or rebooting the FPGA is designed to be short for minimizing the disruption of the operation of the device.
Altera has developed a low-cost structured ASIC implementation of an FPGA without losing the flexibility for prototyping and fast time-to-market. The structured ASIC replaces all the configuration RAM elements with metal interconnects. This dramatically reduces the soft error rate (SER), and the error mitigation for the configuration RAM is not necessary. The overall SER is determined by the user SRAM and logic register, which is very low.
In this study, we report the neutron SER of logic registers for Altera structured ASIC fabricated on 90 nm and 130 nm technologies. The SER test was done at LANSCE neutron facility. The SER results show significant reduction in the error rate for the structured ASIC compared to that of the SRAM-based FPGA with similar logic utilization. The reduction factor is > 1000X for the 90 nm technology and ~100X for the 130 nm technology. The improvement for the 90 nm structured ASIC is due to a novel architecture for the logic elements.
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