"Time-Interleaved ADC Architectures for Space Communications"

Rajan Bedi and Lewis Farrugia
EADS Astrium


The performance being demanded by future telecommunications satellites will only be delivered by advances in mixed-signal processing. Experience has shown that accessing the latest deep sub-micron technologies is difficult due to the low volumes required by space companies. When the major semiconductor vendors are willing to develop hardware, the NRE costs are exorbitant. Moreover, the suitability of the fabrication technology for space flight first needs to be assessed, with vendors often adopting a low-risk approach to radiation testing. 

Faced with such performance, technological, financial and qualification constraints, innovative ideas are required that extend the capability of existing, lower performing COTS hardware to allow satellite manufacturers to support the development of future missions. 

This work reports on the use of time-interleaving ADCs to increase the overall sampling rate and dynamic performance. Time-interleaving with random selection is also considered to deliver a 12-bit, 150 MSPS ADC from a low-power, 50 MSPS QMLV ADC for use on a mobile telecommunications satellite.  

Imperfections in the manufacturing process result in mismatches between the parallel channels. Offset, gain and clock skew between the ADC channels introduce nonlinearity resulting in nonharmonic distortion in the output spectrum. To deliver the performance being demanded by future telecommunications satellites, post-processing DSP techniques must be used to correct for channel mismatches. However, a modern telecommunications satellite has to operate continuously for fifteen years. Changes occur during the lifetime of a payload, e.g. temperature, aging, clock skew and exposure to radiation, will affect the precise matching required by time-interleaving ADCs degrading dynamic performance. This restricts the use of correction techniques to adaptive methods. 

Given the very limited range of ADCs available to satellite manufacturers, the use of time-interleaving with random selection and post-processing DSP techniques to increase the overall sampling rate and dynamic performance, is a relatively cheap way to extend the capability of existing COTS ADCs to support future payloads. Continued scaling of process technologies makes digital processing increasingly expensive.


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