“Single Event Upset (SEU) Testing of the Naval Postgraduate School Configurable Fault-Tolerant Processor (CFTP)”
Joshua Snodgrass, Ron Aikins, Jerry Caldwell, Herschel Loomis, Alan Ross and Melinda Surratt
Naval Postgraduate School
The Naval Postgraduate School (NPS) is building two FPGA-based reconfigurable computing systems, which are scheduled to launch onboard separate LEO satellites in late-2006. Each system contains a pair of identical Xilinx Virtex XQVR600 radiation-hardened FPGAs. These orbital testbeds will be used by researchers at NPS and collaborating organizations to characterize the on-orbit performance of these devices employing various fault-tolerant design concepts. This project is called the Configurable Fault-Tolerant Processor (CFTP).
In preparation for the launch of these space experiments, we have made predictions of radiation-induced SEU response using the proton accelerator at UC-Davis’ Crocker Nuclear Lab and an SEU fault injection simulator at NPS. As expected, the SRAM-based FPGA device is quite sensitive to high-energy proton radiation. Although radiation testing is valuable for determining a device’s sensitivity, it is not suitable for exhaustive SEU studies. For this purpose we have built an SEU simulator that can artificially induce configuration-memory upsets across the entire FPGA. This simulator allows us to compare the relative SEU susceptibility between various design configurations. Radiation testing provides validation for this SEU simulator.
In addition, we conducted proton testing on another CFTP prototype system that uses a Virtex-II XC2V6000 device. A radiation-hardened version of this device is envisioned for use on future-generation CFTP missions.
This paper will briefly describe the CFTP space experiments and then focus on results from radiation testing and simulation. We will present results from the Virtex and Virtex-II proton tests conducted in Nov 2005. We will also highlight a visualization tool that was developed to provide real-time monitoring during radiation testing as well as post-test “playback mode” analysis. The paper will also discuss the SEU simulator system, including the validation effort and results with various test designs.
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