"Verification & Validation: What Can We Learn From Software Engineers?"
Scott Bingham, John Knight, John Lach, and Elisabeth Strunk
University of Virginia
Technology scaling has enabled increasingly complex designs to be implemented on a single integrated circuit. As a result, while the FPGAs of the 1990’s were relatively low-capacity devices, modern FPGAs are capable of implementing extremely complex designs. This rise in FPGA capacity has coincided with their incorporation into a variety of mission- and safety-critical applications, including military defense and aerospace, where designers are increasingly taking advantage of the dynamic reconfigurability of FPGAs.
One of the more significant system changes that has been brought about by increased FPGA densities is their direct interface with elaborate operating environments. Specifications are no longer expressed as Boolean functions that need to be implemented. Rather, they are expressed as user-level functionality that must be provided. In the past this has been the realm of software running on typical microprocessors.
Despite these dramatic changes in the complexity, criticality, and architecture of FPGA-based designs, hardware verification and validation (V&V) methodologies have remained relatively stagnant. Verification – the assurance that a design properly implements its specifications – typically employs traditional methods of simulation and testing. While this was suitable for the low-complexity, low-criticality designs that have been implemented in the past, it has become painfully apparent that more powerful techniques are needed for modern designs. Validation – the assurance that a specification meets its functional and non-functional requirements – has received even less attention. These issues are problematic for hardware design in general, but they become even more acute in FPGA-based design due to the added complexity associated with dynamic reconfiguration.
While FPGA design has only recently had to deal with increasing complexity and criticality, the software community has long wrestled with such issues, yielding rigorous and formal approaches to software V&V. For example, many sophisticated formal languages have been developed that facilitate the precise statement and analysis of specifications. These languages have been shown to: (1) reduce specification defects merely as a result of their use; (2) facilitate effective communication between engineers; and (3) permit a wide variety of analyses that detect a number of specification defects automatically. Formal languages also enable a formal approach to verification. Thus, for example, proofs can be established about desirable properties of an implementation. In some cases, these properties are application independent; for example, freedom from deadlock. In others, properties are derived from the application. Application-specific properties range from simple predicates over application state up to complete satisfaction of a specification by its implementation.
Software techniques are clearly relevant to FPGA-based systems, but not all of the approaches apply, and those that do cannot be used without tailoring them to the needs of FPGAs. This paper provides an introductory analysis of opportunities to leverage approaches currently in use in the software field to create the FPGA V&V methodologies of the future. In particular, we review the state of the art in software V & V and discuss the relevance and applicability of the various techniques to FPGAs.
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