"Dynamic Reconfigurable Computing"

Benjamin C. Brodie, Roger D. Chamberlain, Berkley Shands, and JasonWhite
Exegy, Inc.

Abstract

Reconfigurable computing, typically deployed using Field-Programmable Gate Arrays (FPGAs), is a technology that has often been exploited as an alternative to application-specific integrated circuits.  The advantages include lower upfront fabrication costs and the ability to readily update the functionality through reconfiguration.  What is less common is the use of FPGAs in applications where the functionality is frequently subject to change. 

We have constructed a system that treats the reconfiguration of an FPGA as an operation that is reasonably equivalent to the loading and execution of a binary application on a traditional processor.  The Exegy TextMiner A2000 appliance is a system that incorporates both general-purpose processors and FPGAs as computational resources [1].  It is capable of performing approximate text searches at speeds exceeding 700 MB/s on a single appliance [2]. 

The TextMiner appliance supports three distinct forms of search: exact search, approximate search (which supports character substitutions) [1], and regular expression search [3].  When a user specifies a search query, the system dynamically loads the appropriate configuration into the FPGA(s) and streams the data set through the FPGA(s) to execute portions of the search algorithm. 

This paper will describe the infrastructure we have developed to: a) manage FPGA configuration files (and their associated meta-data), b) move configuration files to/from storage on the FPGA board (which acts as a cache for configuration files normally stored on disk), and c) dynamically reconfigure the FPGA and allocate its resources based on multiple applications’ requests (explicitly supporting multitasking).  We will also describe the decision process by which the software determines which configuration file meets application requirements and is valid (based on the properties of each FPGA).

References

[1]  Mark Franklin, Roger Chamberlain, Michael Henrichs, Berkley Shands, and Jason White, “An Architecture for Fast Processing of Large Unstructured Data Sets.” In Proc. of 22nd Int'l Conf. on Computer Design, October 2004.

[2]  Roger Chamberlain, Berkley Shands, and Jason White, “Achieving Real Data Throughput for an FPGA Co-Processor on Commodity Server Platforms.” In Proc. of 1st Workshop on Building Block Engine Architectures for Computers and Networks, October 2004.

[3]  Benjamin C. Brodie, Ron K. Cytron, and David E. Taylor, “An Architecture for High-Throughput Regular-Expression Pattern Matching.” in Proc. of 33rd Int’l Symp. on Computer Architecture, June 2006.

 

 

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