"Maiden Attempt to Design Reversible FPGAs (FPGAs Based on Reversible Logic)"

Himanshu Thapliyal
International Institute of Information Technology

Abstract

Field programmable gate arrays (FPGAs) are emerging as a promising technology in a number of key areas such as development of high-performance embedded systems, DSP, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, and a number of key important areas. The reason for this stems from the fact that FPGAs can efficiently execute computationally intensive blocks in parallel, and also the availability of dedicated inbuilt functions unit in them such as dedicated 18x18 multipliers makes them suitable for high performance operations. But, the drawback in FPGAs is that they are generally slower than their application-specific integrated circuit (ASIC) counterparts, and consume more power. In order to minimize the power consumption problem and achieve the idealistic goal of high performance low power FPGAs, this paper makes the maiden attempt to design reversible FPGAs (FPGAs designed using reversible logic). In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS (adiabatic logic), quantum computing, nanotechnology, and optical computing. Researchers have shown that for irreversible logic computations, each bit of lost information generates kTln2 joules of heat energy, where k is Boltzmann’s constant and T is the absolute temperature at which the computation is performed.  Reversible circuits do not lose information, and thus kTln2 joules of heat energy will not be dissipated. Furthermore, voltage-coded logic signals have energy of Esig = ˝CV2, and this energy is dissipated whenever the node voltage changes in the irreversible CMOS technology. It is estimated that reversible logic also helps to save energy by using charge recovery logic. Younis has fabricated an 8x8 reversible multiplier array using SCRL gates and measured an energy saving of over 99% over conventional CMOS implementations of the same circuits. Thus, the author proposes the use of reversible logic to design the FPGAs to make them suitable for high performance, low power applications as ideally there is zero power dissipation using reversible logic. In order to have the beginning in this direction, the authors have proposed the designs of reversible CLBs(Configurable Logic Block), which are the key components of FPGAs architectures. The reversible designs of Xilinx XC3000 Series, XC4000 Series, Spartan Series and Virtex Series CLBs have been presented. It is to be noted that CLBs internally consists of LUTs(Look Up Table) and Sequential circuits. Thus, the reversible design of their internal components like sequential circuits has also been presented. The design methodology to design the reversible CLBs, is chosen in way, to design them with minimum number of reversible gates and garbage outputs. It is estimated that the proposed work will provide a new beginning towards the direction of low power high performance reversible FPGAs and attract the attention of researchers to use reversible logic in reconfigurable computing.

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