"Low Cross Section Radiation Tolerant Combinational Logic Structure"

Sterling R. Whitaker, Jody W. Gambles, Lowell H. Miles, Laura Davis and Gary K. Maki
Center for Advanced Microelectronics and Biomolecular Research, University of Idaho


With increased circuit speed and density afforded by fabrication at the 250 nm or less process nodes, single event effects present ever increasing challenges for radiation hard VLSI design. In older processes, single event transient effects could be largely ignored in combinational logic, but no longer.

The proposed combinational logic structure exhibits a greatly reduced Single Event Upset/Single Event Transient sensitive cross sectional area when compared to traditional combinational logic design techniques. In traditional combinational logic, a Single Event Transient (SET) occurring anywhere within the circut area can propagate to be captured in a storage element and result in a Single Event Upset or false output. The new circuit structure is composed of a dual-rail NMOS only pass-transistor network driving a unique cross coupled output buffer. The dual-rail NMOS combinational logic portion is similar in size, and similar/complimentary in transistor topology to a conventional single-rail CMOS design. However, by providing the unique output buffer portion with both Q and Q' outputs from the NMOS only combinational logic network, a very small region of the buffer itself remains the only vulnerable area for propogation of an SET. Although the threat of SET is not completely eliminated, the sensitive cross section has been dramatically reduced.

The proposed combinational logic structure can be incorporated into full custom VLSI, form the basis of standard cell libraries or provide the basis for the combinational logic elements in reprogrammable logic such as an FPGA. These techniques have been applied to harden a multiply-accumulate block for an (8158,7136) low-density parity-check encoder currently being prepared for fabrication in a 250 nm CMOS process.

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