“Partial Reconfiguration Across FPGAs”
Steve Wichman
Redefine TechnologiesAbstract
The FPGA redundancy analysis being performed by Redefine Technologies, along with researchers at the University of Colorado, uses three different redundancy methods to decrease the susceptibility of a spacecraft (on a mission survivability level ) to electronic failures anywhere throughout the spacecraft. This analysis is a NASA Phase I STTR called Triple3 Redundant Spacecraft Subsystems (T3RSS). By using Field Programmable Gate Array (FPGA) chips, we have analyzed the spacecraft-wide benefits of:
Triplicating the logic and RAM on-board each FPGA using Xilinx's Triple Modular Redundancy (TMR) tool;
Triplicating the persistent memory storage and hardware access on-board each subsystem using various methods specific for the space environment; and,
Triplicating the choice of location to run logic (a.k.a. partial reconfiguration across FPGAs), so that subsystem code can run on alternate processors if any component is rendered inoperable due to an electronic failure (radiation, manufacturing, human-error, etc), which actually reduces weight and volume requirements in some instances.
These three methods of triplication should significantly increase the reliability of non-radiation hardened designs, which should allow commercial off-the-shelf (COTS) processing components to be considered as flight critical hardware. The analysis that was performed predicts an increased benefit to any future spacecraft whether it uses radiation hardened components or not. The T3RSS concept has an opportunity to fly on-board a Colorado Space Grant student-designed mission about the 2008 timeframe to prove the design.
The concept of partial reconfiguration across FPGAs proves to be a significant factor that allows designers to maintain 100% mission survivability even using COTS components. The demonstration being provided to NASA Ames Research Center shows that other components in a spacecraft that were designed to do the tasks for their own subsystems can provide the backup capabilities required should a failure render any other component unusable. Redefine Technologies' "code migration" method ensures that all essential tasks will be moved from a non-functioning FPGA to another subsystem's FPGA without a loss of mission and at a significant cost savings both in design and testing time. Eliminating backup components will even reduce weight and volume in some instances on future spacecraft.
This paper outlines the following key issues:
The "Partial Reconfiguration across FPGAs" concept itself
The design choices available to help optimize mission survivability, such as
Percentage of FPGA utilization required
Hardware and memory access across FPGAs
Processing power requirements for each function of each satellite subsystem
Time-multiplexing of reconfigurable modules
Impacts on performance and latency as subsystems are combined
The effects of different mission phases on survivability
The standardization approaches that can be used for redundancy
TMR and scrubbing
Relocatable bitstreams
Baseline IPs for typical satellite functions