"Estimating Cutoff Device Count By Mapping Logic Level Input Transitions To CMOS Device Level : Its Application To Static Power Analysis And Minimization"

N. Venkateswaran, Deepak Srinivasan, and Madhavan Manivannan
WAran Research FoundaTion (WARFT)


On progressing towards the nanotechnology era, the architecture design is constrained by the interconnect dominance with regard to power and delay. Hence the power and performance estimation at the architecture level should be predicted prior to the floor planning and layout phases taking into account the interconnect dominance.  Current techniques focusing on low power design concentrate on dual-Vt, clock gating and device & frequency scaling as potential solutions to bring down the dynamic power component [1][2]. However, as we scale down to beyond 50nm CMOS technology, the static power consumption increases and contributes to almost 50% of the overall power consumption [3]. One technique to minimize this static power element is to simply turn off the power supply to the inactive areas of the chip. While it sounds simple to "turn off" inactive areas of a chip, this heavily relies on the architecture characteristics and can also have a detrimental effect on its performance. Hence there is a strong need to investigate and establish a relationship between the logical input pattern and the number of ‘cut-off’ devices, contributing to the static power.  

This calls for design convergence across logic level abstraction and device level abstraction. In this paper, a mapping methodology has been evolved based on the input pattern, evaluating the cut-off devices’ count. This methodology helps in estimating the peak and average static power directly based on the input transitions. By varying the input pattern, the optimum pattern for which the static power is minimal can be determined. This methodology is applied for designing low power processor control unit which is a Finite State Machine. A multiple tree structure for a given design is constructed treating the output transitions as the root node and the input transitions as leaf nodes. The input patterns are logically partitioned into different groups which have direct impact on the output transitions. By performing graph traversal from the root node to the leaf nodes corresponding to the respective groups, the cut-off devices’ count is established. Appropriate heuristics are developed to minimize the graph traversal complexity. 


  1. "Minimizing power consumption in digital CMOS circuits", AP Chandrakasan, RW Brodersen – Proceedings of the IEEE, 1995.

  2. "A gate leakage reduction strategy for future CMOS circuits," M Drazdziulis, P Larsson-Edefors – Solid-State Circuits Conference, 2003, ESSCIRC’03.

  3. ITRS – Executive Summary – International Technology Roadmap for Semiconductors, 2005.


2006 MAPLD International Conference Home Page