"An Evolvable and Reconfigurable System-on-Chip Architecture for Future Small Satellite Missions"

Xiaofeng Wu and Tanya Vladimirova
Surrey Space Centre, University of Surrey

Abstract

This paper will present the most recent research results on a reconfigurable system-on-chip (SoC) architecture, which is developed at the Surrey Space Centre for future small satellite missions. Spacecraft operate in the unique space environment and are exposed to various types of radiation. Radiation effects can damage the on-board electronic circuits, particularly silicon devices. There is a pressing need for a remote upgrading capability which will allow electronic circuits on-board satellites to self-repair and evolve their functionality. This can be achieved by using modern evolvable hardware technologies, such as the Field Programmable Gate Array (FPGA).  

The FPGAs nowadays are suitable for implementation of complex on-board SoC designs, for example a complete on-board controller (OBC) could be implemented using Xilinx Virtex FPGAs. Soft intellectual property (IP) cores written in hardware description languages and hardwired IP cores available in FPGAs are used or developed for the proposed SoC. The SoC adopts a bus-centric architecture, i.e. all the OBC subsystems are connected to a generic bus. To enable reconfiguration an internal configuration access port (ICAP) is connected to the bus, which allows users to write partial configuration files to the configuration memory. Two examples will be presented to verify the dedicated functionality of the SoC and to demonstrate self-repair and upgrade capabilities.

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