"Encryption of Multispectral Satellite Images with the AES Algorithm"

Roohi Banu and Tanya Vladimirova
Surrey Space Centre, University of Surrey


The advances in microelectronics and the use of COTS (Commercial-Off-the-Shelf) technology enabled to build low cost small satellites, which are affordable by a large number of nations across the world. Small satellites are not only cheaper but require less maintenance and also take less amount of time to build compared to large satellites.  So the demand for small satellites is increasing more and more in recent years. Nowadays satellites provide the society with everything ranging from environmental scientific data to global telecommunications services. This paper focuses on Earth Observation small satellites. Earth Observation (EO) satellites, by definition, observe Earth by taking images with smart imaging sensors (cameras) on-board.

At present, only very few EO satellites are equipped with on-board encryption to protect the images transmitted to the ground station. The encryption algorithms used in present satellite missions are typically proprietary or outdated algorithms like the Data Encryption Standard (DES) rather than algorithms based on the latest encryption standards. The Rijndael algorithm approved as the Advanced Encryption Standard (AES) by the US National Institute of Standards and Technology (NIST) in October 2000 is being adopted by many organizations across the world including the New European Schemes for Signatures, Integrity, and Encryption (NESSIE), the Cryptography Research and Evaluation Committee (CRYPTEC) set up by the Japanese Government and the Consultative Committee for Space Data Systems (CCSDS). 

In this paper we discuss the encryption of multispectral satellite images with the AES algorithm targeting the resource constrained small satellite platform. Computing systems on-board small satellites have limited power and computational resources as in terrestrial embedded systems. With these constraints in mind various optimisation techniques have been applied to the AES algorithm and the implementations have been evaluated in terms of power, throughput and device area. Also the implementations have been carried out using different Xilinx family FPGAs such as Virtex, Virtex2, Virtex 4 and Spatran 3. The results of the experimental work on various FPGA based implementations of AES will be presented and compared.


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